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SL2100
Single chip synthesised broadband converter Datasheet
Features
* * Single chip synthesised broadband solution Compatible with both up converter and downconverter requirements in double conversion tuner applications Compatible with digital and analogue system requirements CSO < -62 dBc, CTB < -64 dBc Extremely low phase noise balanced local oscillator, with I2C bus controlled band switching and with very low fundamental and harmonic radiation Integral fast mode compliant I2C bus controlled PLL frequency synthesiser designed for high comparison frequencies and low phase noise performance Buffered crystal output for pipelining system reference frequency Full ESD protection. (Normal ESD handling procedures should be observed)
DS5365 ISSUE 1.2 November 2001
Ordering Information SL2100B/KG/NP2S (tubes) SL2100B/KG/NP2T (tape and reel)
* * *
*
* *
XTAL CAP XTAL SDA SCL BUFREF Vcc Vee Vee RFINPUT RFINPUTB Vee Vcc Vee IFOUTPUTB
28
SL2100
PUMP DRIVE PORT P0 Vee ADD Vee Vcc LOB LO Vcc Vee Vcc Vee IFOUTPUT
NP28 Figure 1 - Pin allocation noise I2C bus controlled PLL frequency synthesiser. It is intended primarily for application in double conversion tuners as both the up and down converter and is compatible with HIIF frequencies up to 1.4 GHz and all standard tuner IF output frequencies. The device contains all elements necessary, with the exception of local oscillator tuning network, loop filter and crystal reference to fabricate a complete synthesised block converter, compatible with digital and analogue requirements.
Applications
* * * * * * Double conversion tuners Digital Terrestrial tuners Cable Modems Data transmit systems Data communications systems MATV
Description
The SL2100 is a fully integrated single chip broadband mixer oscillator with on-board low phase
1
Datasheet
Quick Reference Data
All data applies with the following conditions unless otherwise stated; a) nominal loads as follows; 1220 MHz output load as in figure (3) 44 MHz output load as in figure (4) b) input signal per carrier of 62 dbuV
SL2100
Characteristic RF input operating range Input noise figure, SSB, 50-860 MHz 860 - 1400 Conversion gain CTB (fully loaded matrix) CSO (fully loaded matrix) P1dB input referred Local oscillator phase noise as upconverter SSB @ 10 kHz offset SSB @ 100 kHz offset Local oscillator phase noise as downconverter SSB @ 10 kHz offset SSB @ 100 kHz offset Local oscillator phase noise floor LO reradiation from RF input fundamental second harmonic third harmonic PLL spurs on converted output with input @ 60 dBuV PLL maximum comparison frequency PLL phase noise at phase detector * dBm assumes a 75 characteristic impedance, and 0 dBm = 109 dBuV c -70 4 -152 TBC c -93 c -115 -136 c -90 c -112 6.5 - 8.5 8.5 - 12 12 c -68 c -65 110 50 - 1400
Units MHz
dB dB dB dBc dBc dBuV
dBc/Hz dBc/Hz
dBc/Hz dBc/Hz dBc/Hz
dBuV dBuV dBuV dBc MHz dBc/Hz
2
SL2100
Datasheet
Functional Description
The SL2100 is a bipolar, broadband wide dynamic range mixer oscillator with on-board I2C bus controlled PLL frequency synthesiser, optimised for application in double conversion tuner systems as both the up and down converter. It also has application in any system where a wide dynamic range broadband synthesised frequency converter is required. The SL2100 is a single chip solution containing all necessary active circuitry and simply requires an external tuneable resonant network for the local oscillator sustaining network. The pin assignment is contained in figure (1) and the block diagram in figure (2). broadband upconverter to a HIIF the output should be differentially loaded, for example with a differential SAW filter, to maximise intermodulation performance. A nominal load is shown in figure (3), which will typically be terminated with a differential 200 load. When used as a narrowband downconverter the output should be differentially loaded, either with a discrete differential to single ended converter as in figure (4), shown tuned to 44 MHz IF, or direct in to a differential input amplifier or SAWF, in which case external loads to Vcc will be required, an example load for 44 MHz application, with a gain of 16 dB is contained in figure (5). The typical IF output impedance as upconverter and downconverter are contained in figures (17) and (18) respectively. In all applications care should be taken to achieve symmetric balance to the IF outputs to maximise intermodulation performance. The typical key performance data at 5V Vcc and 25 deg C ambient are shown in the section headed 'QUICK REFERENCE DATA'.
Converter section
In normal application the RF input is interfaced through appropriate impedance matching and an AGC front end to the device input. The RF input preamplifier of the device is designed for low noise figure, within the operating region of 50 to 1400 MHz and for high intermodulation distortion intercept so offering good signal to noise plus composite distortion spurious performance when loaded with a multi carrier system. The preamplifier also provides gain to the mixer section and back isolation from the local oscillator section. The typical RF input impedance and matching network for broadband upconversion are contained in figures (6) and (7) respectively and for narrow band downconversion in figures (8) and (9) respectively. The input referred two tone intermodulation test condition spectrum is shown in figure (10). The typical input NF is contained in figure (11) and the typical gain in figure (12). The output of the preamplifier is fed to the mixer section which is optimised for low radiation application. In this stage the RF signal is mixed with the local oscillator frequency, which is generated by the on-board oscillator. The oscillator block uses an external tuneable network and is optimised for low phase noise. The typical application as an upconverter is shown in figure (13) and the typical phase noise performance in figure (14). The typical application as a downconverter is shown in figure (15), and the phase noise performance in figure (17). This block interfaces direct with the internal PLL to allow for frequency synthesis of the local oscillator. Finally the output of the mixer provides an open collector differential output drive. The device allows for selection of an IF in the range 30-1400 MHz so covering standard HIIFs between 1 and 1.4 GHz and all conventional tuner output IFs. When used as a
3
PLL frequency Synthesiser
The PLL frequency synthesiser section contains all the elements necessary, with the exception of a reference frequency source and loop filter to control the oscillator, so forming a complete PLL frequency synthesised source. The device allows for operation with a high comparison frequency and is fabricated in high speed logic, which enables the generation of a loop with good phase noise performance. The LO signal from the oscillator drives an internal preamplifier, which provides gain and reverse isolation from the divider signals. The output of the preamplifier interfaces direct with the 15-bit fully programmable divider. The programmable divider is of MN+A architecture, where the dual modulus prescaler is 16/17, the A counter is 4-bits, and the M counter is 11 bits. The output of the programmable divider is fed to the phase comparator where it is compared in both phase and frequency domain with the comparison frequency. This frequency is derived either from the on-board crystal controlled oscillator or from an external reference source. In both cases the reference frequency is divided down to the comparison frequency by the reference divider which is programmable into 1 of 29 ratios as detailed in
Datasheet
figure (19). The typical application for the crystal oscillator is contained in figure (20) The output of the phase detector feeds a charge pump and loop amplifier, which when used with an external loop filter and high voltage transistor, integrates the current pulses into the varactor line voltage, used for controlling the oscillator. The programmable divider output Fpd divided by two and the reference divider output Fcomp can be switched to port P0 by programming the device into test mode. The test modes are described in figure (21). The crystal reference frequency can be switched to BUFREF output by bit RE as described in figure (22)
SL2100
SDA line low during all status byte acknowledge periods to read another status byte. If the controller fails to pull the SDA line low during this period, the device generates an internal STOP condition, which inhibits further reading. Write mode With reference to figure (23), table 1, bytes 2 and 3 contain frequency information bits 214-20 inclusive. Byte 4 controls the synthesiser reference divider ratio, see figure (19) and the charge pump setting, see figure (24). Byte 5 controls the test modes, see figure (21), the buffered crystal reference output select RE, see figure (22) and the output port P0. After reception and acknowledgement of a correct address (byte 1), the first bit of the following byte determines whether the byte is interpreted as a byte 2 or 4, a logic '0' indicating byte 2, and a logic '1' indicating byte 4. Having interpreted this byte as either byte 2 or 4 the following data byte will be interpreted as byte 3 or 5 respectively. Having received two complete data bytes, additional data bytes can be entered, where byte interpretation follows the same procedure, without re-addressing the device. This procedure continues until a STOP condition is received. The STOP condition can be generated after any data byte, if however it occurs during a byte transmission, the previous byte data is retained. To facilitate smooth fine tuning, the frequency data bytes are only accepted by the device after all 15 bits of frequency data have been received, or after the generation of a STOP condition. Read mode When the device is in read mode, the status byte read from the device takes the form shown in figure (23) table 2.
Programming
The SL2100 is controlled by an I2C data bus and is compatible with both standard and fast mode formats. Data and Clock are fed in on the SDA and SCL lines respectively as defined by I2C bus format. The device can either accept data (write mode), or send data (read mode). The LSB of the address byte (R/W) sets the device into write mode if it is low, and read mode if it is high. Tables 1 and 2 in figure (23) illustrate the format of the data. The device can be programmed to respond to several addresses, which enables the use of more than one device in an I2C bus system. Figure (23), table 3 shows how the address is selected by applying a voltage to the 'ADD' input. When the device receives a valid address byte, it pulls the SDA line low during the acknowledge period, and during following acknowledge periods after further data bytes are received. When the device is programmed into read mode, the controller accepting the data must pull the
4
SL2100
Datasheet
Charge pump current The charge pump current can be programmed by bits C1 & C0 within data byte 4, as defined in figure (24). The test modes are defined by bits T2 - T0 as described in figure (21) The general purpose port can be programmed by bits P0; Logic '1' = on Logic '0' = off (high impedance) The buffered crystal reference frequency can be selected by bit RE as described in figure (22)
Bit 1 (POR) is the power-on reset indicator, and this is set to a logic '1' if the Vcc supply to the device has dropped below 3V (at 25C), e.g. when the device is initially turned ON. The POR is reset to '0' when the read sequence is terminated by a STOP command. When POR is set high this indicates that the programmed information may have been corrupted and the device reset to the power up condition. Bit 2 (FL) indicates whether the synthesiser is phase locked, a logic '1' is present if the device is locked, and a logic '0' if the device is unlocked. Programmable features Synthesiser programmable divider Reference programmable divider Function as described above Function as described above.
Test mode
General purpose ports, P0
Buffered crystal reference output select
RF INPUT RF INPUTB OSC TANK TANKB 15 bit Programmable Divider Fpd Charge Pump
IFOUTPUT IFOUTPUTB
PUMP DRIVE
SDA SCL ADD REF OSC Reference Divider Fpd/2 Fcomp PORT P0 I2C Bus Interface BUFREF
XTAL XTALCAP
Figure 2 - SL2100 Block Diagram
5
Datasheet
SL2100
33
OUTPUT
15
Vcc
10 nH 200
SL2100
100nF 14 33 10 nH 200
SAWF B1603
OUTPUTB
Figure 3 - Nominal output load as upconverter into differential SAWF
Vcc 15 pF
15
820 nH
OUTPUT SL2100
14 15 pF 820 nH 10 uH 10 nF
Figure 4 - Nominal output load as downconverter, 44MHz IF
10 nF
OUTPUT
15
Vcc
680 nH
SL2100
100 nF 14 10 nF 680 nH
OUTPUTB
Figure 5 - Output load as downconverter to a differential amplifier
6
SL2100
Datasheet
CH1
S 11
1 U FS SL2100 RF i/p Device 1
1_: 677.38
21 Feb 2000 12:37:59 -502.03 6.3404 pF 50.000 000 MHz
PRm Cor Avg 50 2_: 56.961 -200.02 350 MHz 3_: 22.105 -106.34 650 MHz 4_: 9.5117 -66.727 949.91 MHz
1
2
3 4 START 50.000 000 MHz STOP 950.000 000 MHz
Figure 6 - Typical RF input impedance as broadband upconverter
100nF 9 RF INPUT 200 10
100nF
47nH
Figure 7 - RF input impedance matching network as 50 -860MHz upconverter
7
Datasheet
SL2100
CH1
S 11
1 U FS SL2100 ip impedance pin9
1_: 14.17
1 Mar 2000 10:48:23 -45.779 3.4766 pF 1 000.000 000 MHz
PRm Cor 2_: 14.324 -34.904 1.1 GHz 3_: 14.807 -33.699 1.2 GHz Smo 4_: 16.213 -24.929 1.3 GHz
4 1 3 2
START 950.000 000 MHz
STOP 1 450.000 000 MHz
Figure 8 - Typical RF input impedance as narrow band downcoverter
2.7pF 10 3.9nH 9 10nF
RF INPUT
Figure 9 - RF input impedance matching network as 1.22GHz downconverter
94 dBuV
IIM3 -46dBc
IIM2; -47dBc
48 dBuV 47 dBuV
df f2-f1 f1-df f1 f2 f2+df
Figure 10 - Two tone intermodulation test condition spectrum, input referred
8
SL2100
Datasheet
10 9 8 7 6 5 4 3
Noise Figure(in dB)
Measured with 50 load
2 1 0 0 100 200 300 400 500 600 700 800 900 Input frequency (in MHz)
Figure 11 - Input NF
10 Terminated conversion gain (in dB) 9 8 7 6 5 4 3 2 1 0 0 100 200 300 400 500 600 700 800 900
Measured with 50 load
Input frequency (in MHz)
Figure 12 - Conversion Gain as upconverter
9
Datasheet
SL2100
BB555
1 k
2 pF
Varactor line
Figure 13 - Upconverter oscillator application
95
90
Phase noise
85
80
Measured with 50 load
75
70 0 100 200 300 400 500 600 700 800 900 Input frequency
Figure 14 - Oscillator typical phase noise performance
2.5pF
20
4.3 nH
1 k
21
BB555
Varactor line
Figure 15 - Downconverter oscillator application
10
SL2100
Datasheet
100 98 Phase noise (at 10 kHz offset) 96 94 92 90 88 86
Measured with 50 load
84 82 80 1040
1060
1080
1100
1120
1140
1160
1180
1200
1220
LO frequency
Figure 16 - Typical phase noise performance as downconverter
CH1 S 11 B1 PRm Cor Avg 3 Smo 1_: 5.0039 -66.137 1 GHz 2_: 6.373 -51.047 1.15 GHz 3_: 9.3398 -44.512 1.25 GHz 1 U FS 4_: 8.7988 19 Jan 2001 11:04:45 -35.773 3.1778 pF 1 400.000 000 MHz
4
3 2 START 1 000.000 000 MHz 1 STOP 1 400.000 000 MHz
Figure 17 - Typical IF output impedance as upconverter, single-ended
CH1 S 11 1 U FS B2 PIN14 5V PRm Cor Avg 2 Smo 1_: 2.5804 k -994.38 10 MHz 2_: 1.1366 k -1.3737 k 40 MHz 3_: 488.88 -1.0823 k 70 MHz 4_: 283.34 23 Jan 2001 14:03:25 -868.59 1.8323 pF 100.000 000 MHz
4 1 2 3
START 10.000 000 MHz
STOP 100.000 000 MHz
Figure 18 - Typical IF output impedance as downconverter, single-ended
11
Datasheet
R4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 R2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 R1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 R0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Ratio 2 4 8 16 32 64 128 256 Illegal state 5 10 20 40 80 160 320 Illegal state 6 12 24 48 96 192 384 Illegal state 7 14 28 56 112 224 448
SL2100
Figure 19 - Reference division ratios
12
SL2100
Datasheet
XTALCAP 47pF 47pF 4MHz XTAL
Figure 20 - Crystal oscillator application (typical)
XTALCAP 47pF 47pF XTAL SL2100 (DOWN)
4MHz
10pF
NC
XTALCAP SL2100 (UP) XTAL
10nF
10k
Figure 21 - Crystal oscillator application in dual conversion architecture
13
Datasheet
T2 0 0 0 0 1 1 T1 0 0 1 1 0 0 T0 0 1 0 1 0 1 Test mode description Normal operation Charge pump sink * Status byte FL set to logic '0' Charge pump source * Status byte FL set to logic '0' Charge pump disabled * Status byte FL set to logic '1' Normal operation and Port P0 = Fpd/2 Charge pump sink * Status byte FL set to logic '0' Port P0 = Fcomp Charge pump source * Status byte FL set to logic '0' Port P0 = Fcomp Charge pump disabled * Status byte FL set to logic '1' Port P0 = Fcomp Figure 21 - Test modes
SL2100
1
1
0
1
1
1
* clocks need to be present on crystal and LO inputs to enable charge pump test modes and to toggle status byte bit FL
RE 0 1
BUFREF output disabled, high impedance enabled Figure 22 - Buffered crystal reference output select
14
SL2100
Address
Datasheet
MSB 1 0 27 1 T2 1 214 26 C1 T1 0 213 25 C0 T0 0 212 24 R4 X 0 211 23 R3 X MA1 210 22 R2 X MA0 29 21 R1 RE LSB 0 28 20 R0 P0 A A A A A Byte 1 Byte 2 Byte 3 Byte 4 Byte 5
Programmable divider Programmable divider Control data Control data
Table 1 - Write data format (MSB is transmitted first)
MSB Address Programmable divider 1 POR 1 FL 0 0 0 0 0 0 MA1 0 MA0 0 LSB 1 0 A A Byte 1 Byte 2
Table 2 - Read data format (MSB is transmitted first)
A MA1,MA0 214-20 C1-C0 R4-R0 T2-T0 P0 POR FL X : : : : : : : : : : Acknowledge bit Variable address bits (see Table 3) Programmable division ratio control bits Charge pump current select (see figure (24)) Reference division ratio select (see figure (19)) Test mode control bits (see figure (21)) P0 port output state Power on reset indicator Phase lock flag 'Don't care'
MA1 0 0 1 1
MA0 0 1 0 1
Address input voltage level 0-0.1Vcc Open circuit 0.4Vcc - 0.6 Vcc # 0.9 Vcc - Vcc
Table 3 - Address selection
# Programmed by connecting a 30 k resistor between pin and Vcc Figure 23 - Data Formats
15
Datasheet
Current in A C1 0 0 1 1 C0 min 0 1 0 1 +-98 +-210 +-450 +-975 Figure 24 - Charge pump current typ +-130 +-280 +-600 +-1300
SL2100
max +-162 +-350 +-750 +-1625
16
SL2100
Datasheet
Electrical Characteristics
Test conditions (unless otherwise stated) Tamb = -40 to 85C, Vee= 0V, Vcc=5V+-5% These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage unless otherwise stated. Characteristic Supply current pin min typ 90 max 120 units mA Conditions IF outputs will be connected to Vcc through the differential load as in figures (3)&(4) Operating condition only Operating condition only Operating condition only
Input frequency range Output frequency range Composite peak input signal
50 30 97
1400 1400
MHz MHz dBuV
All synthesiser related spurs on IF Output Upconverter application Input frequency range 50
-60
dBc
Within channel bandwidth of 8 MHz and with input power of 60 dBuV
860
MHz dB
Input impedance Input return loss Input Noise Figure 6
75
See figure (6), With input matching network as in figure (7) See figure (11), with input matching network as in figure (7) Differential voltage gain to 200 load on output of SAWF as in figure (3), see figure (12) 50-860 MHz
9.5
dB
Conversion gain
9
dB
Gain variation across operation range Gain variation within channel Through gain CSO CTB IPIP22T IPIP32T
-1
+1
dB
0.5
dB
Channel bandwidth 8 MHz within operating frequency range 45-1400 MHz Measured with 128 channels at 62 dBuV Measured with 128 channels at 62 dBuV See note (2) See note (2)
-20 -62 -64 137 116
dB dBc dBc dBuV dBuV
17
Datasheet
Characteristic IPIM22T IPIM32T LO operating range 1 pin min typ max -47 -46 2.3 units dBc dBc GHz Conditions See note (2), see figure (10) See note (2), see figure (10)
SL2100
Maximum tuning range 0.9 GHz determined by application Application as in figure (13), see figure (14)
LO phase noise, SSB @ 10 kHz offset @ 100 kHz offset LO phase noise floor IF output frequency range LO and harmonic leakage to RF input Fundamental 2nd harmonic 3rd harmonic IF output impedance Downconverter application Input frequency range 1000 1400 MHz dB 14 dB 64 81 49 dBuV dBuV dBuV 1 -90 -110 -85 -106 -136 1.4 dBc/Hz dBc/Hz dBc/Hz GHz
Application as in figure (13)
To device input
See figure (17)
Input impedance Input return loss Input Noise Figure 12
75
See figure (8) With input matching network as in figure (9) Tamb=27C, with input matching network as in figure (9) Differential voltage gain to 50 load on output of impedance transformer as in figure (5) Channel bandwidth 8 MHz within operating frequency range 45-1400 MHz See note (2) See note (2), see figure (10) Maximum tuning range determined by application, see note (4)
18
Conversion gain
12
dB
Gain variation within channel Through gain IPIP32T IPIM32T LO operating range 1 117 -20
0.5
dB
dB dBuV -46 2.3 dBc GHz
SL2100
Datasheet
pin min typ max units See figure (16) -94 -116 -92 -112 -136 100 dBc/Hz dBc/Hz dBc/Hz MHz Application as in figure (13) Application as in figure (15) Conditions
Characteristic LO phase noise, SSB @ 10 kHz offset @ 100 kHz offset LO phase noise floor IF output frequency range IF output impedance SYNTHESISER SDA, SCL Input high voltage Input low voltage Input high current Input low current Leakage current Hysterysis SDA output voltage
See figure (18)
I2C 'Fast mode' compliant 3 0 5.5 1.5 10 -10 10 0.8 0.4 0.6 V V uA uA uA V V V kHz See figure (24), Vpin = 2V Isink = 3 mA Isink = 6 mA Input voltage = Vcc Input voltage = Vee Vcc=Vee
SCL clock rate Charge pump output current
400
Charge pump output leakage Charge pump drive output current Crystal frequency Recommended crystal series resistance Oscillator temperature stability Oscillator supply voltage stability 0.5
+-3
+-10
nA
Vpin = 2V
mA
Vpin = 0.7V
2 10
20 200
MHz
See figure (20) for application 4 MHz parallel resonant crystal
TBC TBC
ppm/C ppm/V
19
Datasheet
Characteristic External reference input frequency External reference drive level Phase detector comparison frequency Equivalent phase noise at phase detector pin min 2 0.2 typ max 20 0.5 units MHz Vpp Conditions
SL2100
Sinewave coupled through10 nF blocking capacitor Sinewave coupled through 10 nF blocking capacitor
4
MHz
-152 -158
dBc/Hz dBc/Hz 32767
SSB, within loop bandwidth 2 MHz 250 kHz
Local oscillator programmable divider division ratio Reference division ratio Output port sink current leakage current Buffered REF/COMP output output amplitude output impedance Address select Input high current Input low current
240
See figure (19) See note (3) 2 10 mA uA Vport = 0.7 Vport =Vcc AC coupled 0.0625-20 MHz, 0.35 250 Vpp See figure (23) table (3) 1 -0.5 mA mA Vin=Vcc Vin=Vee Enabled by bit RE=1 and default state on power-up
Notes (1) All power levels are referred to 75 and 0 dBm = 109 dBuV (2) Any two tones within RF operating range at 94 dBuV beating within band, with output load as in figure (3) (3) Port powers up in high impedance state (4) To maximise phase noise the tuning range should be minimised and Q of resonator maximised. The application as in figure (15) has a tuning range of 200 MHz.
20
SL2100
Datasheet
Vcc
RF
9
XTAL 2 1
RFB
10
XTALCAP
200A
RF Inputs
VREF
Reference Oscillator
Vcc
500K LO
500K
20
500K SCL/SDA
*
LOB 21
ACK
* On SDA only
Oscillator Inputs
SDA/SCL (pins 3 and 4)
IF OUTPUT
15 14 IF OUTPUTB P0 26
IF Outputs
Output port
21
Datasheet
SL2100
Vcc Vcc 28 PUMP 120K ADD 220 24 40K 27 DRIVE
Loop amplifier
ADD Input
Vcc
5 ENABLE/ DISABLE
BUFREF
1mA
BUFREF ouput
22
SL2100
Datasheet
Absolute Maximum Ratings
All voltages are referred to Vee at 0V Characteristic Supply voltage RF input voltage All I/O port DC offsets SDA, SCL DC offsets Storage temperature Junction temperature Package thermal resistance, chip to case Package thermal resistance, chip to ambient Power consumption at 5.25V ESD protection 2 -0.3 -0.3 -55 min -0.3 max 7 117 Vcc+0.3 6 150 150 20 units V dBuV V V C C C/W Vcc = Vee to 5.25V Differential, ac coupled inputs conditions
85
C/W
630
mW kV Mil-std 883B method 3015 cat1
23
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